(Hong Kong)
Product Summary
| Datasheets |
IDT7024S/L |
|---|---|
| Product Photos |
IDT84 Series |
Standard Package 
|
15 |
| Category | Integrated Circuits (ICs) |
| Family | Memory |
| Series | - |
|
Packaging
|
Tube
|
| Format - Memory | RAM |
| Memory Type | SRAM - Dual Port, Asynchronous |
| Memory Size | 64K (4K x 16) |
| Speed | 20ns |
| Interface | Parallel |
| Voltage - Supply | 4.5 V ~ 5.5 V |
| Operating Temperature | -40°C ~ 85°C |
| Package / Case | 84-LCC (J-Lead) |
| Supplier Device Package | 84-PLCC (29.21x29.21) |
| Other Names |
IDT7024L20JI IDT7024L20JI-ND |
Diagrams
HIGH-SPEED IDT7024S/L
4K x 16 DUAL-PORT
STATIC RAM
◆ IDT7024 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
◆ M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
◆ Interrupt Flag
◆ On-chip port arbitration logic
◆ Full on-chip hardware support of semaphore signaling
between ports
◆ Fully asynchronous operation from either port
◆ Battery backup operation—2V data retention
◆ TTL-compatible, single 5V (±10%) power supply
◆ Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆ Green parts availble, see ordering information
Functional Block Diagram
Features
◆ True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
◆ High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
◆ Low-power operation
– IDT7024S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7024L
Active: 750mW (typ.)
Standby: 1mW (typ.)
◆ Separate upper-byte and lower-byte control for multiplexed
bus compatibility
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/WL
BUSYL
A11L
A0L
2740 drw 01
UBL
LBL
CEL
OEL
I/O8L-I/O15L
I/O0L-I/O7L
CEL
OEL
R/WL
SEML
INTL M/S
R/WR
BUSYR
UBR
LBR
CER
OER
I/O8R-I/O15R
I/O0R-I/O7R
A11R
A0R
R/WR
SEMR
INTR
CER
OER
(2)
(1,2) (1,2)
(2)
12
12
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
|---|---|---|---|---|---|---|---|---|---|---|
 |
 7024L20JI |
Other |
|
Data Sheet |
Negotiable |
|
||||
|
7024L20JI8 |
Other |
|
Data Sheet |
Negotiable |
|
||||
